Fully parallel fractional motion estimation for H.264/AVC encoder
Fractional motion estimation always takes much processing time because of variety of motion vectors and two-step sequential half-quarter pel. In this paper, we propose the architecture of fractional engine in fully parallel manner. Instead of sequential processing two-step of half-quarter refinement, integer-half-quarter pel is processed in parallel manner in order to double the speed as well as the throughput. Using Chartard 0.18 μm CMOS 1P5M technology, the proposed architecture is implemented with 412k logic gates and achieves the throughput of 255 kMBs/s supporting HDTV1080p 30 fps when operating at the frequency of 220MHz.
integer fractional motion estimation half-quarter Del: H.264/A VC
Nam Thang Ta Jun Rim Choi Jae Hoon Kim Seon Cheol Hwang Shi Hye Kim
School of Electrical Engineering and Computer Science Kyungpook National University Daegu,Republic o Induk University
国际会议
上海
英文
2835-3838
2009-11-20（万方平台首次上网日期，不代表论文的发表时间）