Full System Simulation and Verification Framework

摘要：

In this paper, we propose a framework to develop highperformance system accelerator hardware and the corresponding software at system-level. This framework is designed by integrating a virtual machine, an electronic system level platform, and an enhanced QEMU-SystemC. The enhancement includes a local master interface for fast memory transfer, and an interrupt handling hardware for software/hardware communication that enables full system simulation. Finally, the PAC DSP core is used as examples to demonstrate the proposed framework for full system simulation.

作者: Jing-Wun Lin Chen-Chieh Wang Chin-Yao Chang Chung-Ho Chen Kuen-Jong Lee Yuan-Hua Chu Jen-Chieh Yeh Ying-Chuan Hsiao

作者单位: Institute of Computer and Communication Engineering National Cheng Kung University,Tainan,Taiwan SoC Technology Center Industrial Technology Research Institute,Taiwan

会议类型: 国际会议

会议名称: The Fifth International Conference on Information Assurance and Security(第五届信息保障与安全国际会议)

会议地点: 西安

会议语种:英文

页码: 165-168

在线出版日期: 2009-08-18（万方平台首次上网日期，不代表论文的发表时间）