ECC-Cache: A Novel Low Power Scheme to Protect Large-Capacity L2 Caches from Transiant Faults
With dramatic scaling in feature size of VLSI technology, the capacity of on-chip L2 cache increases rapidly, how to guarantee the reliability of large capacity L2 cache has become an important issue. However, increasing the reliability of L2 cache tends to reduce its performance and brings more power consumption. This paper presents ECC-Cache, a novel low power fault-tolerant architecture which divided the traditional method of detecting and correcting errors using some uniform coding scheme into two steps, and uses a hybrid method which protects clean data and dirty data in different way to enhance the reliability of L2 cache. This paper also compares the performance and power consumption of ECC-Cache with that of some other proposed schemes, experimental results show that ECC-Cache is effective to guarantee the reliability of large-capacity L2 cache, while bringing little impact to system performance and power consumption. We find that ECC-Cache performs better than the uniform-ECC scheme adopted in some widespread used commercial processors and some proposed schemes in other papers. Compared with the cache which has no protection, ECC-Cache only consumes 3％ to 6％ additional power and degrades performance no more than 2％.
cache architecture fault tolerant transient fault reliability
Guanghui Liu
Department of Computer National University of Defense Technology ChangSha 410073,China
国际会议
The Fifth International Conference on Information Assurance and Security(第五届信息保障与安全国际会议)
西安
英文
193-199
2009-08-18（万方平台首次上网日期，不代表论文的发表时间）