Advanced High Density Interconnect Materials and Techniques
The trend in micro/nanosystems is to be lighter, smaller and cheaper. At the same time there is a prodigious push for increasing functionalities. Such demands can only be fulfilled by progressively higher density integrated devices and circuits. With 2D IC reaching its physical limitation soon, 3D IC has attracted tremendous attentions and interests worldwide. For either 2D or 3D IC, the interconnection and packaging will be one of the major challenges for the development and commercialization of micro/nanosystems. Flip chip at chip level and wafer-level have the advantages of having the lowest possible inductance per lead, highest frequency response speed as well as the lowest cross talk and simultaneous switching noise. Challenges arise when interconnection method of flip chip is gradually growing into the mainstream in the integration and packaging industry where the issue of size becomes increasingly critical for interconnection and pitches. Therefore, the development of new interconnection materials and techniques is necessary to meet the ever-stringent requirements of mechanical, thermal and electrical properties of interconnection when the interconnection dimension and pitch size are reduced to very fine scales. Furthermore, such advanced interconnection materials and techniques can also be used to stack 3D IC. In this paper, the development of novel lead-free solder nanocomposites, room to low temperature Cu-Cu and Au-Au bonding, and carbon nanotube interconnection techniques will be reported. The developed micro/nanointerconnection techniques can be easily adopted by the industry to realize high density and multifunctional integration and packaging.
J. Wei S. M. L. Nai X. F. Ang K. P. Yung
Singapore Institute of Manufacturing Technology,71 Nanyang Drive, Singapore, 638075 Singapore Institute of Manufacturing Technology, 71 Nanyang Drive, Singapore, 638075
国际会议
北京
英文
6-13
2009-08-10（万方平台首次上网日期，不代表论文的发表时间）