Research on Synthesis Parameter Real-time Scheduling Algorithm on Multi-core Architecture
Nowadays, multi-core processors, which have multiple processing units on a single chip, are becoming mainstream due to their superior performance and power characteristics. Meanwhile, the design of real time system on multi-core processors is being confronted with a new challenge. However, the traditional real time scheduling algorithms, such as EDF and Pfair, easily lead to many tasks missing their deadlines on multi-core processors in overload condition. Aiming at this problem, a new scheduling algorithm which adopts synthesis parameter judging priority method to extend Pfair scheduling algorithm is proposed. The experiment results show that the deadline miss rate (DMR) of synthesis parameter scheduling algorithm is lower than that of traditional scheduling methods. Consequently, the synthesis parameter scheduling algorithm improves the schedule utilization of real-time tasks and increase real time system performance on multi-core processor effectively.
multi-core schedule synthesis parameter DMR
Benhai Zhou Jianzhong Qiao Shukuan Lin
College of Information Science and Engineering,Northeastern University,Shenyang Liaoning Province 11 College of Information Science and Engineering,Northeastern University,Shenyang Liaoning Province 11
国际会议
2009年中国控制与决策会议(2009 Chinese Control and Decision Conference)
广西桂林
英文
5116-5120
2009-06-17（万方平台首次上网日期，不代表论文的发表时间）