High-speed I/O Buffer Modeling for Signal-integrity-based Design of VLSI Interconnects
Digital I/O buffers play an important role for the signal integrity (SI) simulation and timing analysis of high-speed VLSI interconnect networks, which often require the consideration of electromagnetic (EM) effects. In this paper, we give an overview of the recent advances in efficient macromodeling of nonlinear digital I/O buffers, including equivalent-circuit-based and neural-network-based approaches. The detailed equivalent circuit models are accurate but computationally slow. On the other hand, the simplified equivalent circuit models are fast but only provide limited accuracy. The neural-network-based models are good alternatives to those equivalent-circuit-based models, maintaining a good overall performance in terms of accuracy and speed. We demonstrate the neural-network-based approaches through an example of modeling a commercial high-speed integrated circuit (IC) device and its application to the SI simulation of high-speed interconnect networks.
Yi Cao Qi-Jun Zhang
Department of Electronics,Carleton University,Ottawa,ON,K1S 5B6,Canada
国际会议
Progress in Electromagnetics Research Symposium 2009(2009年电磁学研究新进展学术研讨会)(PIERS 2009)
北京
英文
1383-1386
2009-03-23（万方平台首次上网日期，不代表论文的发表时间）