A Study of Stress technology for 65nm Generic CMOS technology

摘要：

For deep sub-100nm CMOS technology, the stress level impacts transistor performance significantly. In this paper, we present the investigation results of stress technology in a 65 nm generic process. We studied some mobility enhancing technologies such as Stress-Memorization Technology (SMT) and Dual Stress Liner (DSL) process in a conventional 65 nm Generic CMOS process. The transistor performance with different stress layers and stress levels are reported. The experimental results show that SMT and higher stress level tensile ESL (Etch-Stop Layer) improve NMOS performance while compressive ESL improve PMOS significantly. For the required-device performance, the stress layer and stress architecture should be carefully optimized. The stress technology reported in this paper has been successfully implemented in the production of 65 nm generic process.

作者: Xinfu Liu Wenjun Dai Xing Yu Louis Lim Bin Xue Boyong He

作者单位: Department of ACT,Chartered Semiconductor Manufacturing LTD,738406,Singapore Department of ACE,United Microelectronics Corporation,519528,Singapore

会议类型: 国际会议

会议名称: ISTC/CSTIC2009中国国际半导体技术研讨会

会议地点: 上海

会议语种:英文

页码: 37-70

在线出版日期: 2009-03-19（万方平台首次上网日期，不代表论文的发表时间）