Shallow Trench Isolation Stress Effect on NMOS Transistor Leakage, SRAM Standby Current and VCCMIN

摘要：

Three key process steps in shallow trench isolation (STI) technology: STI liner oxide, STI to AA step height, and annealing temperature. Their impacts on NMOS devices leakage, SRAM standby current and Vccmin have been studied. MOSFET transistors off state current (Ioff) and body current (IB) were measured at varied length of diffusion (LOD) for STI stress effect analysis. For low power NMOSFET transistors, IB is seen to be the main part of Ioff and has a strong correlation to the processes that modulates STI stress. The experiment results show that the STI stress level can be much reduced by decreasing STI oxide RTA temperature and liner ox thickness, hence leading to lower IB and SRAM standby current. It is also demonstrated that SRAM Vccmin can be improved～10％ by STI stress reduction.

作者: Jianhua Ju Jay Ning Eric Liu ZhaoXu Shen Allan Zhou Jinhua Liu Daniel Deng Cathy Ren Susu Wei Hokmin Ho

作者单位: Logic Technology Development Center,SMIC (BJ) Beijing 100176,P. R. of China

会议类型: 国际会议

会议名称: ISTC/CSTIC2009中国国际半导体技术研讨会

会议地点: 上海

会议语种:英文

页码: 117-122

在线出版日期: 2009-03-19（万方平台首次上网日期，不代表论文的发表时间）