A High Performance 80V Smart LDMOS Power Device Based on Thin SOI Technology
The high junction leakages, circuit latched issues, and high parasite capacitances preset in junction isolation technology can be improved by the thin SOI (Silicon-On-Insulator) technology. A CMOS compatible SOI technology will be in of the technologies used in the future roadmap of LDMOS devices. A CMOS compatible thin SOI LDMOS (Lateral Double-diffused MOSFET) device, with 0.18 micron gate length, 0.02 micron gate oxide and 3 micron N-drift region, is proposed to achieve the optimal (BVoff) off-state breakdown voltage and on-state resistance (Ron) values. The characteristics of the proposed LDMOS device are verified by the two-dimensional process simulator TSuprem-IV and the device simulator Medici. The simulated results have shown that a device performance at the range of BVoff, 80V, and Ron, 190 mohmmm2, is achieved. The on-state breakdown voltage is measured at 70V with an excellent safe operating area (SOA) performance for the drain source current versus on-state breakdown voltage.
Gene Sheu Shao-Ming Yang Yu-Shan Hsu
Computer Science and Information Technology (CSIE) Department of Asia University,Taichung County,41354,Taiwan
国际会议
上海
英文
123-128
2009-03-19（万方平台首次上网日期，不代表论文的发表时间）