Use FPGA Configuration Memory For Backend Defect Capture
In deep sub-micro era, with the increase of circuit complexity, more and more metal layers are used for inter-connection. Chance for killing defects coming from backend metal layers is significantly increased. Especially for lower metal layers with smaller features, defects on them may be difficult detected by conventional current-based isolation techniques. Therefore development of defect monitoring method becomes critical for wafer fabrication yield improvement. SRAM-based FPGA is already well known for front-end defect capture capability. Studies also demonstrate its capability to capture defects on higher interconnection layers with specially designed test pattern. 1 With the dense and segmented data-line structure, the configuration memory can be used as a much simple approach to monitor defects on lower metal layer In this paper, we will go through the architecture of a 90nm FPGA and its configuration SRAM. By study the electrical data-line failure signature, we will discuss the corresponding isolation techniques. Finally we will show some defects captured by this methodology.
G. Qian J. J. Shi
Xilinx Asia Pacific,5 Changi Business Park Vista,Singapore 486040
国际会议
上海
英文
173-197
2009-03-19（万方平台首次上网日期，不代表论文的发表时间）