Study on Bit Line TiCl4 TIN Process Optimization for Stack DRAM IDDS Standby Failure Improvement

摘要：

Dynamic Random Access Memory (DRAM) plays an important role in semiconductor industry. For 0.13um stack DRAM (D13) process, Bit line (BL) is a critical loop and acts as a contact between active area (AA) and periphery area. Normally, BL consists of BL glue layer Ti/TiN and BL W and TiCl4 has been used for D13 BL glue layer Ti/TiN deposition. D13 suffers electrical drain-to-drain standby (IDDS) failure, meaning junction electrical leakage. It has been found that BL glue Ti/TiN has strong influence on AA Ti diffuse. In addition, IDDS standby failure is enhanced with deeper TiSix formation. In this study, we present the effect of TiCl4 glue TiN films quality on D13 IDDS standby failure.

作者: Liang Chen Zhi-Chao Li Xing-Hua Song Lei Xu Yi-Hui Lin Hsueh-Hung Wei Paul-Chang Lin

作者单位: SMIC Semiconductor Manufacturing International Corp,18 Zhangjiang Road,201203,Shanghai,China SMIC (Semiconductor Manufacturing International Corp),18 Zhangjiang Road,201203,Shanghai,China

会议类型: 国际会议

会议名称: ISTC/CSTIC2009中国国际半导体技术研讨会

会议地点: 上海

会议语种:英文

页码: 587-591

在线出版日期: 2009-03-19（万方平台首次上网日期，不代表论文的发表时间）