Ezploratory NEMS-CMOS Hybrid Devices for Post CMOS era
Si device technology is facing the limit of physical scaling for several reasons such as a power management, an increasing cost of physical scaling, and a variability of nano scale devices. Furthermore, the physical scaling alone does not provide strong benefits on performance as in the past technology generations due to increasing parasitic components (capacitance and resistance) and rising chip temperature. Yet, the demands for increased functionality still exist. Thus, to continue increasing the level of integration, it is important to find a way 1) to control the power consumption and dissipation, 2) to increase the utilization of existing devices within the chip, and 3) to improve the efficiency of interconnect. Hybridization of nano electro mechanical switch (NEMS) with CMOS technology has been proposed to reduce the power consumption in some circuit modules by one to two orders of magnitude with a minimal cost at performance. NEMS-CMOS hybrid device technology appears to be an attractive option in terms of power management, but there are not enough learning on true nano scale NEMS device, which can be readily integrated with Si CMOS technology. In this talk, various options for NEMSCMOS hybridization and associated challenges in materials and devices will be reviewed.
B.H. Lee
Department of Material Science and Engineering,Gwangju Institute of Science and Technology Oryong 1,Buk-gu,Gwangju,Korea,500-712
国际会议
上海
英文
857-862
2009-03-19（万方平台首次上网日期，不代表论文的发表时间）