Multi-channel high-speed CMOS image acquisition and pre-processing system

摘要：

A new multi-channel high-speed CMOS image acquisition and pre-processing system is designed to realize the image acquisition, data transmission, time sequential control and simple image processing by high-speed CMOS image sensor. The modular structure design, LVDS and ping-pong cache techniques used during the designed image data acquisition sub-system design ensure the real-time data acquisition and transmission. Furthermore, a new histogram equalization algorithm of adaptive threshold value based on the reassignment of redundant gray level is incorporated in the image preprocessing module of FPGA. The iterative method is used in the course of setting threshold value, and a redundant graylevel is redistributed rationally according to the proportional gray level interval. The over-enhancement of background is restrained and the feasibility of mergence of foreground details is reduced. The experimental certificates show that the system can be used to realize the image acquisition, transmission, memory and pre-processing to 590MPixels/s data size, and make for the design and realization of the subsequent system.

关键词： FPGA image acquisition ping-pong cache technique adaptive threshold value histogram equalization redundant gray level

作者: Chun-feng |Sun Feng Yuan Zhen-liang Ding

作者单位: Dept. of Automation Testing and Control, Harbin Institute of Technology, Harbin, 150001, China

会议类型: 国际会议

会议名称: 第五届仪器科学与技术国际学术会议(ISIST 2008)Fifth International Symposium on Instrmentation Science and Technology

会议地点: 沈阳

会议语种:英文

页码: 1-6

在线出版日期: 2008-09-15（万方平台首次上网日期，不代表论文的发表时间）