Design of Reusable and Flezible Test Access Mechanism Architecture for System-on-Chip
Recent advances in IC design methods and manufacturing technologies have led to the integration of a complete system onto a single IC, called system on chip (SoC). These system chips offer advantages such as higher performances, lower power consumption, and decreased size and weight, when compared to their traditional multichip equivalents. However, testing such core-based SoCs poses a major challenge for system integrators. Modular testing of embedded cores in a system-on-chip (SoC) is now recognized as an effective method to tackle the SoC testing problem. In this paper we present an approach to design a TAM architecture and its associated test schedule using a fast and efficient heuristic. The test access mechanism architecture is responsible for the transportation of the test data from the system inputs to the core inputs and from the core outputs to the system outputs and also it could be very useful testing multifrequency cores in SoC.
G.Rohini S.Salivahanan
St.Josephs College of Engineering,Chennai 600 119,India SSN College of Engineering,Kalavakkam 603 110,India
国际会议
Progress in Electromagnetics Research Symposium 2008(2008年电磁学研究新进展学术研讨会)(PIERS 2008)
杭州
英文
1-6
2008-03-24（万方平台首次上网日期，不代表论文的发表时间）