Design of a Low Power, High Performance BICMOS Current-limiting Circuit for DC-DC Converter Application
A low power, high performance current-limiting circuit implemented in 0.6um BICMOS process, which has been successfully applied to the chip of high efficiency, wide input voltage range DC-DC boost switch power management chip, is presented. The circuit as the core sub-block of the chip consists of current-limiting comparator, soft starting and slop compensation. The dynamic bias and slop compensation technology in current-limiting comparator is adopted to improve the performance and to reduce power consume. In this paper, the deign methodology and process of the circuit is analyzed in detail. The simulation and test results based HSPICE show: under the power supply of 3.3 V, the circuit has the gain of 117 dB and low quiescent current of 15 UA.
Hongbo Ma Quanyuan Feng
Institute of Microelectronics, Southwest Jiaotong University, ChengDu 610031, China
国际会议
Progress in Electromagnetics Research Symposium 2007(2007年电磁学研究新进展学术研讨会)(PIERS 2007)
北京
英文
854-859
2007-03-26（万方平台首次上网日期，不代表论文的发表时间）