An Improved BSIM4 Model for 0.13-μm Gate-length High Linearity CMOS RF Transistors
An improved BSIM4 large-signal model for 0.13-1m gate-length high linearity CMOS RF transistors is presented in this paper. The field-plate technology functions the improvements in linearity and 1/f noise of 0.13-1m CMOS devices was in our past investigation. To accurately accomplish the CMOS field-plate device model, an improved BSIM4 model with RLC networks representing the parasitic effects of transmission line and lossy substrate has been adopted for microwave applications up to 40 GHz. Good agreement has been realized between the measured and modeled results in terms of devices DC curves, S-parameters, 1/f noise, and power performance.
Chien-Cheng Wei Chia-Shih Cheng Shao-Wei Lin Yong-Jhih Chen Hsien-Chin Chiu Wu-Shiung Feng
Department of Electronic Engineering, Chang Gung University Kwei-Shan, Tao-Yuan, Taiwan, China
国际会议
Progress in Electromagnetics Research Symposium 2007(2007年电磁学研究新进展学术研讨会)(PIERS 2007)
北京
英文
1052-1056
2007-03-26（万方平台首次上网日期，不代表论文的发表时间）