Low Power Dissipation SEU-hardened CMOS Latch

摘要：

This paper reports three design improvements for CMOS latches hardened against single event upset (SEU) based on three memory cells appeared in recent years. The improvement drastically reduces static power dissipation, reduces the number of transistors required in the VLSI, especially when they are used in the Gate Array. The original cells and the new improved latches are compared. It is shown that the new latch-NDICE latch has the best compositive capability and the best SEU immunity.

作者: Yuhong Li Suge Yue Yuanfu Zhao Guozhen Liang

作者单位: Beijing Microelectronics Technology Institute, 100076, China

会议类型: 国际会议

会议名称: Progress in Electromagnetics Research Symposium 2007(2007年电磁学研究新进展学术研讨会)(PIERS 2007)

会议地点: 北京

会议语种:英文

页码: 1995-1999

在线出版日期: 2007-03-26（万方平台首次上网日期，不代表论文的发表时间）