Design and Simulation of RSFQ/RISC Computer System
We present a novel asynchronous RSFQ digital circuit, test-Timed RSFQ digital circuit and system(TT),in this paper. With this asynchronous approach,data is transferred in a delay-insensitive fashion to avoid the overhead of global clock distribution and the timing uncertainty. According to the scheme, the timing signal of the logic module is generated by a test logic module. The delay module can be removed from our circuit which should be used in previous asynchronous circuits. Finally, the simulation results for the Test-Timed data processing pipeline based on TT scheme are presented.
Zhong-Hai Zhang Bo-Ran Guan
Xidian University,China;Hangzhou Dianzi University,China Hangzhou Dianzi University,China
国际会议
Progress in Electromagnetics Research Symposium 2005(2005年电磁学研究新进展学术研讨会)(PIERS 2005)
杭州
英文
583-586
2005-08-22（万方平台首次上网日期，不代表论文的发表时间）