Design and Implement for Test in a Complez System on Chip
With the increasing complexity and chip scale of SoC, DFT (Design-for-test) has become a more important and difficult process. A system-level DFT strategy for a SoC based on 32-bit RISC CPU is presented. According to the characteristic of different parts of SoC, test solutions for digital logic, SRAM and CPU Core in the SoC are discussed. The test methods include internal scan design, MBIST, BSD and function test. The results show the higher fault coverage and smaller area overhead are gotten.
DFT scan chain ATPG MBIST SoC
Jinghe Wei Zhiguo Yu Zongguang Yu Longxing Shi
The 58th Research Institute of CETC Wuxi, China Southeast University Nanjing, China
国际会议
北京
英文
127-129
2009-10-27（万方平台首次上网日期，不代表论文的发表时间）