An IP Wrapper Design for System-on-a-Chip Test
Testing core-based systems is a major challenge. The major factor is that the accessibility of the cores and blocks is greatly reduced. Furthermore, the system designer might have a restricted knowledge of the core internals due to the protection of Intellectual Property(IP) of the cores. This paper proposes an IP wrapper design method for System-on-a-Chip test based on self schedule and parallel BIST for SOC (MBSSP-BIST)1. MBSSP-BIST can effectively improve SOC test efficiency, but it requires a specific IP wrapper. This paper designs the structure of the wrapper, which can operate in three modes: normal work mode, core test mode and isolated mode. The experiment shows that the area and performance overhead of the wrapper are small and the function is right. The synthesis result shows that the area and performance overheads are only about 5％.
System-on-a-Chip Testing Wrapper
Danghui Wang Deyuan Gao
Computer Science and Technology College,Northwestern Polytechnical University, Xian, Shaanxi, China
国际会议
第八届国际测试技术研讨会(8th International Symposium on Test and Measurement)
重庆
英文
135-138
2009-08-01（万方平台首次上网日期，不代表论文的发表时间）