A Novel Test Methodology for Design of an Embedded Synchronous dual-read/write port SRAM with Configurable Capacity

摘要：

A novel test methodology for design of a 4K embedded synchronous dual-read/write port SRAM with configurable capacity is proposed. In this paper, the hardware/software co-design methodology is used to design a 4K embedded synchronous dual-port SRAM. The advantage of this approach, about efficiency and fault coverage, is dicussed. The discussions prove that the approach can accelerate the design obviously. Eight 4K embedded synchronous dual-read/write port SRAM in a system are fabricated using 0.25um CMOS technology. The device operates at 200MHz with a 2.5 V supply. The test of the embedded SRAM die after manufacture is successful.

关键词： dual-port SRAM MARCH CE FPGA Block RAM

作者: Lei Wang Zhiping Wen Lei Chen Huabo Sun Shuo Wang

作者单位: Beijing Microelectronics Tech.Institution(BMTI) No.2.Siyingmen N.Rd Donggaodi Fengtai District, Beijing, China, 100076

会议类型: 国际会议

会议名称: 第八届国际测试技术研讨会(8th International Symposium on Test and Measurement)

会议地点: 重庆

会议语种:英文

页码: 204-207

在线出版日期: 2009-08-01（万方平台首次上网日期，不代表论文的发表时间）