Modeling and Testing the Interconnect Resources of SRAM-Based FPGAs

摘要：

A novel methodology for the derivation of test configurations (TCs) automatically for application-independent manufacturing testing of the interconnect resources of SRAM-based FPGAs is presented. First, we model the local/global interconnect resources of SRAM-based FPGAs using adjacency graph and bipartite graph respectively. Then, we use a modified simulated annealing algorithm to solve the graph coloring problem, in order to obtain the minimal TCs for the interconnect resources testing. To validate the proposed methods, the interconnect resources model and TC derivation method is applied to our BMTI BQV50 FPGA1, which is fabricated using 0.25um CMOS technology and is compatible to Xilinx XCV50 FPGA. A minimal number of TCs is obtained automatically.

关键词： local/global interconnect resources testing automatically TC derivation adjacency and bipartite graph modified simulated annealing algorithm

作者: Shuo Wang Zhiping Wen Lei Chen Lei Wang Zengrong Liu

作者单位: Beijing Microelectronics Tech.Institution (BMTI) No.2.Siyingmen N.Rd Donggaodi Fengtai District, Beijing, China, 100076

会议类型: 国际会议

会议名称: 第八届国际测试技术研讨会(8th International Symposium on Test and Measurement)

会议地点: 重庆

会议语种:英文

页码: 295-298

在线出版日期: 2009-08-01（万方平台首次上网日期，不代表论文的发表时间）