Analysis and Optimization of Domino OR Gate with Sleep Transistor Based on Wavelet Neural Networks

摘要：

A model for analyzing and optimizing the active power, the leakage power and the delay of the domino OR gates with the sleep transistor based on wavelet neural networks in 45 nm CMOS technology is proposed. By studying the impact of the sleep transistor, the model can successfully forecast the nonlinear changing of the active power, the leakage power and the delay of the different inputs domino OR gates. The simulation results for verification indicate that the forecasting model can be well applied in VLSI design with accuracy ratio of more than 90％.

关键词： domino OR gate power delay WNN

作者: WANG Jinhui WU Wuchen Yuan Ying Yuan Ying GONG Na

作者单位: VLSI and System Lab, Beijing University of Technology, Beijing, China, 100124 College of Electronic and Informational Engineering, Hebei University, Baoding, China, 071002

会议类型: 国际会议

会议名称: 第八届国际测试技术研讨会(8th International Symposium on Test and Measurement)

会议地点: 重庆

会议语种:英文

页码: 1578-1581

在线出版日期: 2009-08-01（万方平台首次上网日期，不代表论文的发表时间）