DFG Model for JTAG Architecture for Mized Signal SoC

摘要：

A design method of JTAG architecture for MSSoC testing is addressed in this paper. Mixed signal SoC (MSSoC) is used for application design more and more, such as biomedical device, sensor and wireless sensor network devices, control module, instrument modules, and so on. In MSSoC analog and digital are combined together to implement some special function. How to analyze such complex device is a challenge for design of MSSoC. JTAG is a useful technology for electronic system testing. To use JTAG technology in MSSoC testing model has to be built at first. This paper employs the DFG method to establish the model testing for MSSoC with JTAG. With the model the system time character and simplest architecture for JTAG application in MSSoC could be designed and analyzed.

关键词： JTAG MSSoC

作者: Lv Caixia Liu Jia Wang Shuying Li Zheying Li Shuo

作者单位: Institute of Micro Electronic Application Tech, Beijing Union University, Beijing 100101 Dept.of Microelectronics and Information Technology Royal Institute of Technology,Stockholm, Sweden

会议类型: 国际会议

会议名称: 第八届国际测试技术研讨会(8th International Symposium on Test and Measurement)

会议地点: 重庆

会议语种:英文

页码: 2194-2197

在线出版日期: 2009-08-01（万方平台首次上网日期，不代表论文的发表时间）