Design and Realization of DPLL used in SDH equipment Clock

摘要：

A novel digital phase locked loop(DPLL) used in SDH equipment Clock is proposed in this paper. The output frequency of this DPLL is 155.520MHz which is the most used timing frequency in SDH transmission system. The time resolution of phase detector in traditional DPLL is low, and then it is not fit for the DPLL in 155.520Mbit/s system. In our new DPLL, the phase detector is implemented with a time-to-digital converter whose time resolution is 200ps. With the improvement of phase detector, the DPLL shows excellent performance. The DPLL meets the requirement given in ITU-T Recommendation G.813, and has been used in our SDH transmission system.

关键词： digital phase locked loop SDH time-to-digital converter

作者: Wu Wenjun Tang Guilin Huang Zhiping Liu Chunwu

作者单位: Mechatronic and Automatization School, National University of Defense Technology,Changsha, China

会议类型: 国际会议

会议名称: 第八届国际测试技术研讨会(8th International Symposium on Test and Measurement)

会议地点: 重庆

会议语种:英文

页码: 3045-3048

在线出版日期: 2009-08-01（万方平台首次上网日期，不代表论文的发表时间）