Architecture Design of a Comparator for SAR ADC
A novel high-speed and high-precision voltage comparator has been proposed. In the comparator design, the Switched Operational Amplifier technique is adopted in the pre-amplifier stage to reduce the power consumption. The proposed voltage comparator is designed for 1MHz 12-bit SAR ADC under TSMC 180nm 1P6M CMOS technology. The resolution of the voltage comparator is 0.2mV under the 1.8V power supply with the sample rate of 20MS/s.
High-precision low power dissipation Switched Operational Amplifier
XIU Limei LI Zheying
Institute of Micro-electronic Application Tech, Beijing Union University, Beijing, China, 100101
国际会议
第八届国际测试技术研讨会(8th International Symposium on Test and Measurement)
重庆
英文
3166-3169
2009-08-01（万方平台首次上网日期，不代表论文的发表时间）