A Synchronous High-Speed Dual-Channel Data Collecting System for Radar

摘要：

A data collecting system for radar receiver is proposed. Two AD9480 chips are employed to synchronously sample data on two channels of radars receiver. DDR SDRAM is used to cache the sampled data. Two 8-bit sampled data from two channels are combined into a 16-bit-length data, which is sent to DDR cache by a FPGA interface controller. The system is applied successfully on different types of radar and shows good performance in achieving high-speed synchronous sampling and high data rate transmission.

关键词： Data collection Radar receiver AD9480 FPGA DDR

作者: Huang Jinbo Tang Yonggang Li Zhong Liang

作者单位: Guilin Airforce Academy, Guilin,China,541003

会议类型: 国际会议

会议名称: 第八届国际测试技术研讨会(8th International Symposium on Test and Measurement)

会议地点: 重庆

会议语种:英文

页码: 3173-3175

在线出版日期: 2009-08-01（万方平台首次上网日期，不代表论文的发表时间）