Research on All Digital Phase Locked Loop with TDC and DAC
An all Digital Phase Locked Loop (DPLL) which is operable at very low frequency about 1Hz is introduced. This DPLL contains a digital phase frequency detector, an embedded micro-controller and a Digital to Analog Converter (DAC). A precisely Time to Digital Converter (TDC) chip is used to measure the time interval between the reference signal and the under test signal. A processor is embedded to convert the time interval to phase difference between the two signals, take out the control policy calculation, change the results to digital codes, sent it to Digital to Analog Converter to control the low-cost Oven Controlled Crystal Oscillator(OCXO) and keep the phase constant. A adjacent averaging filter based on numeric algorithm and software processing is adopted. The benefit of the TDC Phase Detector (PD) is that it can easily measure the phase difference at very low frequency. The DPLL is characteristic of its simple structure, flexible control method, high phase tracking precision and excellent loop performance, etc. It makes sure from the experiment results of the GPS disciplined OCXO frequency standard that the design method is correct.
DPLL TDC DAC GPS frequency standard
Cui Baojian Zhao Haiying Zhou dehai Zhang dan
No.92493 Branch 89, Huludao, Liaoning, China, 125000
国际会议
第八届国际测试技术研讨会(8th International Symposium on Test and Measurement)
重庆
英文
3182-3185
2009-08-01（万方平台首次上网日期，不代表论文的发表时间）