Boundary-Scan Controller Design of Digital Circuit Based on FPGA

摘要：

Based on the research of the IEEE Std 1149.1 and the SOPC technology, a kind of boundary-scan test controller with NIOS II CPU is designed by putting reusable IP cores and user-designed IP core together. The design of a synchronous finite state machine which is the key part of the user-designed IP core is described in detail. Furthermore, the user-designed boundary-scan test bus congtroller IP core provides an important module for SOPC system.

关键词： IEEE Std 1149.1 boundary-scan test controller IP core SOPC

作者: WANG Yuefang ZHENG Weidong ZHANG Xinxi LI Yong

作者单位: Academy of Armored Forces Engineering, Beijing, China, 100072

会议类型: 国际会议

会议名称: 第八届国际测试技术研讨会(8th International Symposium on Test and Measurement)

会议地点: 重庆

会议语种:英文

页码: 3210-3213

在线出版日期: 2009-08-01（万方平台首次上网日期，不代表论文的发表时间）