The Design of Uninterrupted Data Transmission System Based on the Interface Chip of PCI9054 Ezpanding FIFO

摘要：

Introduced the performance, bus arbitration and data transmission characteristic of the PCI bus interface chip PCI 9054. Proposed a realization of uninterrupted data transmission system based on the interface chip of PCI 9054 expanding FIFO. As the PCI 9054 interior FIFO is mainly used for data read/write control purpose with limited capacity, it can not fulfill the data transmission requirement for hardware-in-the-loop simulation system. This paper uses ALTERA FPGA to realize expanding asynchronous FIFO. The ALTERA EPF10K10 FPGA contains three EABs, when EAB is used for storage purpose, each EAB provide 2K memory capacity and can be used as FIFO. The FIFO module can be programmed using EAB without any exterior element. In this paper, the expanding FIFO has a capacity of 4 KB, for the waveform data storage and plays as buffer in D/A conversion period. The solution uses separate modules. FPGA (Field Programmable Gate Array)is used as the system control center. PCI bus data transmission uninterruptedly was achieved with FIFO(First In First Out) technique and DMA(Direct Memory Access) transmission mode. The problem of data transmission intermittence caused by computer interruption during the process of data transmission in hardware-in-the-loop simulation system is solved, the uninterrupted simulation data with reliability can then be provided for hardware-in-the-loop simulation system.

关键词： PCI bus hardware-in-the-loop simulation FPGA FIFO DMA

作者: ZHANG Zhi-an ZHANG Ying YANG jian

作者单位: ZNDY of Ministerial Key Laboratory, Nanjing University of Science& Technology, Nanjing, Jiangsu,Chin ZNDY of Ministerial Key Laboratory, Nanjing University of Science& Technology, Nanjing, Jiangsu,Chin

会议类型: 国际会议

会议名称: 第八届国际测试技术研讨会(8th International Symposium on Test and Measurement)

会议地点: 重庆

会议语种:英文

页码: 3265-3268

在线出版日期: 2009-08-01（万方平台首次上网日期，不代表论文的发表时间）