A Parallel Architecture of Bit-split State Machine for Pattern Matching Engine

摘要：

Bit-split state machine, which is memory efficient, is a partial state machine split from a whole one constructed by using Aho-Corasick algorithm. When implemented on FPGA, the throughput of multi- pattern matching engine based on bit-split state machine doesnt fulfill the requirement of detection speed. A parallel architecture of bit-split state machine is proposed. The new architecture can make the bit-split state machine process data in parallel, not one byte per clock in the traditional architecture, which results in an acceleration of the speed. The engine is divided into some sub-engines which consist of 8 bit-split state machines. Some key issues related to the implement on FPGA are discussed. Experiment results show that the engine with parallel architecture has high throughput with little resource consumption.

关键词： pattern matching bit-split state machine parallel architecture

作者: LIU Wei GUO Yuanbo ZHANG Jie LI Jingfeng

作者单位: Institute of Electronic Technology, the PLA Information Engineering University, Zhengzhou Henan,China,450004

会议类型: 国际会议

会议名称: 第八届国际测试技术研讨会(8th International Symposium on Test and Measurement)

会议地点: 重庆

会议语种:英文

页码: 3404-3407

在线出版日期: 2009-08-01（万方平台首次上网日期，不代表论文的发表时间）