A Bus-converter IP Core
An IP core about Protocol Conversion among UART, IIC and SPI is designed in this paper. First the system structure is introduced, and then the design methods of each module about the IP core are illustrated in detail. The IP core can make the buses convert among them and communicate with data by extending it on hardware. Finally the function of IP core is simulated under the software, and is verified through designing a FPGA prototype testing system.
Inter-IC Bus Serial Peripheral Interface Universal Asynchronous Receiver /Transmitter
LU Ming LI Zheying NIU Wenliang
Institute of Micro-electronic Application Tech, Beijing Union University, Beijing, China, 100101
国际会议
第八届国际测试技术研讨会(8th International Symposium on Test and Measurement)
重庆
英文
3428-3431
2009-08-01（万方平台首次上网日期，不代表论文的发表时间）