A Functional Enhancement Methodology to JTAG Controller in Complez SOC
Based on one complex SOC chip, one functional enhancement methodology to standard IEEE P1149.1 JTAG controller is proposed in this paper. With the enhanced features, all test functions including stuck-at scan, at-speed scan, memory BIST and high-speed physical layer tests can be controlled by the JTAG controller besides traditional boundary scan tests, and further on-chip debug features are also integrated in this enhanced JTAG controller. Therefore, the chip costs can be reduced, and the software development and debug can be facilitated with the enhanced JTAG controller.
SOC JTAG boudnary scan test DFT on-chip debug
Guo Jian-min Luo De-lin
Department of Automation, Xiamen University Xiamen, 361005, China
国际会议
第四届国际计算机新科技与教育学术会议(2009 4th International Conference on Computer Science & Education)
南京
英文
1128-1131
2009-07-25（万方平台首次上网日期，不代表论文的发表时间）