SOPC based flezible architecture for JPEG enconder
The new generation of field programmable gate array (FPGA) technologies enables an embedded processor intellectual property (IP) and an application IP to be integrated into a system-on-a-programmable-chip (SOPC) developing environment. Therefore, in this paper, we present an efficient HW/SW codesign architecture for JPEG encoder and its FPGA implementation. It consists of a NIOS II processor that controls the scheduling of a set of specialized processors that perform the discrete cosine transform (DCT), quantization (Q), RLC, Huffman encoder. The architecture also includes pre-processing modules for the input video signal from the camera and interfaces for the external video memory and the LCD. The JPEG encoder supports the baseline JPEG mode and an efficient architecture for the 2-D DCT is suggested to reduce the chip size. The whole design is described in verilog HDL language, verified in simulations and implemented in Cyclone II EP2C35 FPGA. Finally, the encoder has been tested on a NIOS II development board and some experimental results are demonstrated.
JPEG SOPC FPGA Nios II processor IP-core
Cai Ken Liang Xiaoying Liu Chuanju
Information College Zhongkai University of Agriculture and Engineering Guangzhou, China School of Bi Guangdong Womens Polytechnic College Guangzhou, China Information College Zhongkai University of Agriculture and Engineering Guangzhou, China
国际会议
第四届国际计算机新科技与教育学术会议(2009 4th International Conference on Computer Science & Education)
南京
英文
1151-1154
2009-07-25（万方平台首次上网日期，不代表论文的发表时间）