Fast Gate-level Simulation and Power Analysis For High Performance Microprocessor
With the advance of VLSI technology, power consumption of chips has become a major concern in the state of art CMOS circuits design. Among all kinds of previous power analysis methods, the gate-level power analysis can give a relatively accurate result and has been commonly used. However, the simulation speed is very low due to large amount switching activity records for all gate-level cells. In this paper, we proposed a novel method to accelerate gate-level power simulation and estimation. The experimental results based on actual gate-level netlist of Godson-2 processor1 have shown that the proposed method can improve simulation speed by about 20 times compared with traditional gate-level power calculation, and the error of power analysis result is less than 5％.
Power analaysis gate-level simulation Godson-2 processor
Yiwei Zhang Ge Zhang
Department of Information and Technology University of International Relations Beijing, China Institute of Computing Technology Chinese Academy of Sciences Beijing, China
国际会议
第四届国际计算机新科技与教育学术会议(2009 4th International Conference on Computer Science & Education)
南京
英文
1155-1158
2009-07-25（万方平台首次上网日期，不代表论文的发表时间）