Hardware Implementation of a High Speed Floating Point Multiplier Based on FPGA

摘要：

The hardware implementation of a high speed floating point multiplier with pipeline architecture based on FPGA is presented in the paper. In the design of the floating point multiplier, the utilization of a new Radix-4 Booths encoding algorithm, the improved 4:2 compression structure and summation circuit is made to implement the compression of the partial products, and the sum and carry vectors are added by a final carry look-ahead adder to obtain the product. The timing simulation results show that the floating point multiplier can be steadily run at the frequency of 80 MHz. The multiplier has been adopted in the FFT processor successfully.

关键词： FPGA Booth’s algorithm Partial Product Compression Pipeline Floating-point Multiplier

作者: Gong Renxi Zhang Shangjun Zhang Hainan Meng Xiaobi Gong Wenying Xie Lingling Huang Yang

作者单位: School of Electrical Engineering,Guangxi University, Nanning 530004, China Department of Electronic Engineering,Guilin College of Aerospace Technology, Guilin 541004,China

会议类型: 国际会议

会议名称: 第四届国际计算机新科技与教育学术会议(2009 4th International Conference on Computer Science & Education)

会议地点: 南京

会议语种:英文

页码: 1902-1906

在线出版日期: 2009-07-25（万方平台首次上网日期，不代表论文的发表时间）