An Improved Design Method for Multi-bits Reused Booth Multiplier
In order to solve the question for the 32-bit multiplier to do a variety of bit-length multiplication fast in the form of reusing resource on the FPGA, radix-4 booth modified algorithm is studied, and a bit-length controller is designed to control some bits, partial product generator and fast adders structure are improved, so as to reuse most of the hardware resource in 8-bit or 16-bit multiplication. The multiplier works with not only 32-bit but also two 16-bit or four 8-bit data at one clock, ensures the speed and saves the chip area at the same time.
booth multiplier reuse multi-bits
Qian Yi HAN Jing
Department of Information Science and Technology Taishan University Taian, China Department of Information Engineering Taishan Medical University Taian, China
国际会议
第四届国际计算机新科技与教育学术会议(2009 4th International Conference on Computer Science & Education)
南京
英文
1914-1916
2009-07-25（万方平台首次上网日期，不代表论文的发表时间）