A Practical Scheduling Architecture and Its Implementation for Input-Queued Switches
To increase both the capacity and the processing speed for Input-Queued (IQ) Switches, a Fair Scalable Scheduling Architecture (FSSA) has been proposed. By employing FSSA comprised of several chips of cascaded sub-scheduler, a large-scale high performance network scheduler can be realized without the capacity limitation of monolithic device. In this paper, we present an improved scheduling algorithm named FSSA_DI instead of the ordinary FSSA. Using the proposed algorithm where a distributed iteration scheme is employed, the scheduler performance can be improved and the processing time can be reduced as well. Simulation results show that FSSA_DI achieves better performance on average delay and throughput under heavy loads compared to other existing algorithms. Moreover, a practical 64×64 FSSA using FSSA_DI algorithm is implemented with 4 Xilinx Vertex-4 FPGAs. Measurement results show that the data rates of our solution can be up to 800 Mbps and the tradeoff between performance and hardware complexity has been solved peacefully.
Qingsheng Hu Chen LIU Hua-An Zhao
Institute of RF- & OE-ICs, Southeast University, Nanjing, China College of Optical and Electronic Engr., Nanjing University of Posts and Tele., China Dept.of Computer Science and Electrical Engineering, Kumamoto University, Japan
国际会议
2009国际通信电路与系统学术会议(ICCCAS 2009)(2009 International Conference on Communications，Circuits and Systems)
成都
英文
177-181
2009-07-23（万方平台首次上网日期，不代表论文的发表时间）