Frequency-Overscaling DSP Circuit Design with Reduced-Precision Redundancy and Subword Detection Processing

摘要：

Reduced-precision redundancy (RPR) technique has recently developed for voltage-overscaling (VOS) low-power DSP circuit design and soft error tolerance. In this paper, we combine the RPR technique with a frequency-overscaling (FOS) technique and propose a subword-detection processing technique to increase the speed of a DSP circuit. The proposed techniques can improve the clock speed with acceptable noise degradation by employing a reduced-precision replica of main DSP module. We design and implement an FOS FFT processor with the RPR and SDP techniques. The simulation results show that the proposed techniques can improve the SNR performance by 34.5 dB when the operating frequency is overscaled to 1.21 times of the maximal achievable frequency.

作者: Ying-Kuang Cheng Yuan-Hao Huang

作者单位: Department of Electrical Engineering, National Tsing-Hua University, Taiwan China Institute of Communications Engineering and the Department of Electrical Engineering, National Tsing

会议类型: 国际会议

会议名称: 2009国际通信电路与系统学术会议(ICCCAS 2009)(2009 International Conference on Communications，Circuits and Systems)

会议地点: 成都

会议语种:英文

页码: 431-434

在线出版日期: 2009-07-23（万方平台首次上网日期，不代表论文的发表时间）