A 400MS/s 10-bit Current-steering D/A Converter

摘要：

This paper presents a 10-bit 400MS/s CMOS current-steering digital-to-analog converter (DAC) for video applications. The proposed DAC adapts segmented architecture, composed of 6 MSBs unary and 4 LSBs binary-weighted cells. An improved current switching scheme is developed to compensate the systematic error further. The post-layout simulation results show that the converter achieves a spurious-free dynamic range (SFDR) up to 71.5dB and a 1LSB settle time smaller than 500ps at 400MS/s. The full-scale output current is 20mA with 3V power supply for analog part, while the digital part of the chip operates at 1.8V. The active area is 0.2 mm2 in a standard 1P-6M 0.18μm CMOS process.

作者: Yannan Ren Fule Li Chun Zhang Zhihua Wang

作者单位: Institute of Microelectronics of Tsinghua University, Beijing, China

会议类型: 国际会议

会议名称: 2009国际通信电路与系统学术会议(ICCCAS 2009)(2009 International Conference on Communications，Circuits and Systems)

会议地点: 成都

会议语种:英文

页码: 533-536

在线出版日期: 2009-07-23（万方平台首次上网日期，不代表论文的发表时间）