High Voltage SOI SJ-LDMOS on Composite Substrate

摘要：

A new super junction LDMOS (SJ-LDMOS) on partial silicon-on-insulator (SOI) with composite substrate is presented in this paper. The thin super junction structure on the buried oxide (BOX) provides the surface low on-resistance path, which is attributed to the heavy doping trait of SJ. The N-buffer layer is introduced under the BOX to sustain vertical voltage, which reduces the substrate-assisted depletion (SAD) effect. In addition, the N-buffer layer increases the vertical breakdown voltage without increasing the thickness of BOX. The proposed device preserves the isolation advantage of SOI device because the N-buffer layer is self-isolation. Numerical simulation results indicate that a breakdown voltage of 280 V for the proposed device with drift length of 15 μm, comparing with a breakdown voltage of 150 V for conventional SOI SJ-LDMOS suffering for the SAD effect.

作者: Wenlian Wang Bo zhang Zhaoji Li

作者单位: State key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronics Science and technology of China, Chengdu, China

会议类型: 国际会议

会议名称: 2009国际通信电路与系统学术会议(ICCCAS 2009)(2009 International Conference on Communications，Circuits and Systems)

会议地点: 成都

会议语种:英文

页码: 614-616

在线出版日期: 2009-07-23（万方平台首次上网日期，不代表论文的发表时间）