Throughput Estimation for ModelSim Simulator Tool Based HW/SW Co-Verification System

摘要：

Efficient and reliable verification system is requested for a System-on-a-chip (SOC) design before it is committed to production. The intention of the paper is to judge whether our hardware/software (HW/SW) co-verification system can handle SOC verification and provide the necessary performance in terms of co-verification speed and throughput. A Finite Impulse Response (FIR) filter is utilized as a Device-under-Test (DUT) to compare pure software simulation, ModelSim simulator in this case, and HW/SW co-verification approaches to decide on whether the HW/SW co-verification system can work or not. Experiment result demonstrates the more complicated SOC is, the greater the potential speedup of the co-verification approach over software simulation is. However, the communication between software and hardware in HW/SW co-verification system is a major bottleneck, which may offset the acceleration achieved by moving large computation from software side to hardware side.

作者: A.W.Ruan Y.B.Liao P.Li W.C.Li W.Li

作者单位: State Key Laboratory of Electronic Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

会议类型: 国际会议

会议名称: 2009国际通信电路与系统学术会议(ICCCAS 2009)(2009 International Conference on Communications，Circuits and Systems)

会议地点: 成都

会议语种:英文

页码: 1014-1018

在线出版日期: 2009-07-23（万方平台首次上网日期，不代表论文的发表时间）