Joint Equalization Technique and Special Spacing Rules for Link Design
Achieving high link speed and reliability is a key challenge in Network-on-chip(NoC) design. To address the challenge,, we propose the equalization scheme and the joint equalization technique and special spacing rules solution for improving the communication speed and reliability for NoC links in the paper. The proposed equalizer employs a variable threshold inverter whose switching threshold is modified as a function of past output of the links. The experiment results for a 10-mm 32-bit link in 0.13um CMOS process technology show that 1.28× speedup is achievable by equalization alone with 1% area overhead. The simulation results show that the joint equalization and increasing spacing of the uncoded link can reduce 50%delay and save 42% power only with 50% area overhead compared with the minimum-spaced uncoded links .The BER of the links is improved from 10-5 to 10-24.
Lei Li Jianhao Hu Chun He Wanting Zhou
Key Laboratory of Communication of UESTC
国际会议
2009国际通信电路与系统学术会议(ICCCAS 2009)(2009 International Conference on Communications,Circuits and Systems)
成都
英文
1042-1046
2009-07-23(万方平台首次上网日期,不代表论文的发表时间)