An Improved Pattern Generation for Built-in Self-test Design Based on Boundary-scan Reseeding

摘要：

Reseeding is an effective method to reduce test redundancy, i.e., to reduce test length in Built-in Self-test (BIST) design. In general reseeding method, the seeds were saved in a ROM, however, bringing about higher hardware overhead. Managed by Test Access Port (TAP) controller, an improved reseeding method proposed in this paper adopts boundary scan architecture to reseed the test pattern generation for BIST with the calculated seeds. Simulation and demonstration results based on selected logic circuit and ISCAS’85 benchmark circuits show that the boundary-scan reseeding can work correctly and effectively, that is, the test length can be largely reduced without losing fault coverage, and thereby, the reduction of hardware overhead is achieved as expectedly.

作者: Enmin Tan Wenwu Qian Yan Li

作者单位: School of Electronic Engineering, Guilin University of Electronic Technology, Guilin, China Institute of Information Technology of Guilin University of Electronic Technology, Guilin, China

会议类型: 国际会议

会议名称: 2009国际通信电路与系统学术会议(ICCCAS 2009)(2009 International Conference on Communications，Circuits and Systems)

会议地点: 成都

会议语种:英文

页码: 1082-1086

在线出版日期: 2009-07-23（万方平台首次上网日期，不代表论文的发表时间）