Ezploiting Power-Area Tradeoffs in High-Level Synthesis through Dynamic Functional Unit Allocation
The increasing power consumption levels of integrated circuits (ICs) have become a major concern of the semiconductor industry. Excessive power dissipation causes overheating, which can lead to soft errors or permanent damage. It also limits battery life in portable equipments. High power consumption can be reduced by properly increasing area. However, arbitrarily large area, namely high number of functional unit (FU) in high-level view, dramatically increases IC cost. This paper describes a new dynamic-power aware High Level Synthesis (HLS) data path approach that considers dynamic FU allocation whilst attempting to minimize area, power, or make a tradeoff between them. The experimental results have shown that when the area is nearly same, our approach delivers a 5.99％ reduction in power consumption. And when the power consumption is nearly same, a 11.81％ reduction in total FU area is got. The optimal power-area tradeoffs values can be obtained by adjusting power and area ratios.
Feng Wu Ning Xu Junbo Yu Fei Zheng Jinian Bian
School of Computer Science and Technology, Wuhan University of Technology, Wuhan 430070, China Department of Computer Science and Technology, Tinghua University, Beijing 100080, China
国际会议
2009国际通信电路与系统学术会议(ICCCAS 2009)(2009 International Conference on Communications，Circuits and Systems)
成都
英文
1092-1096
2009-07-23（万方平台首次上网日期，不代表论文的发表时间）