System-level Synthesis: From Specication to Transaction Level Models
With design complexities increasing daily, the multi-core community is entertaining the idea of increasing the level of abstraction to transaction-level modeling (TLM) and design. However, the proper denition, style or semantics of TLM is not clear. Nor is it clear how to synthesize or verify TLMs. In this paper, we will introduce several TLM models and dene their semantics. This formalism will allow us to dene design decisions and corresponding model transformations that can be used to transform one model into another. These transformations and renements are the enabler for automatic synthesis and verication on TLM. We will also discuss the algorithms and ow for model transformation according to the OSI network layers and show how to build tools with inputs and outputs at transaction level. We will conclude with preliminary tools and results that promise a productivity gain of several orders of magnitude.
Daniel D.Gajski
Center for Embedded Computer Systems University of California, Irvine Irvine, CA 92697-2625
国际会议
2009国际通信电路与系统学术会议(ICCCAS 2009)(2009 International Conference on Communications，Circuits and Systems)
成都
英文
1134-1138
2009-07-23（万方平台首次上网日期，不代表论文的发表时间）