Rule-based Equivalence Checking of System-level Design Descriptions

摘要：

This paper presents our study on rule-based equivalence checking of system-level design descriptions. The rule-based equivalence checking proves the equivalence of two system-level design descriptions by applying equivalence rules in a bottom-up manner. In this paper, we first introduce our intermediate representation of system-level design, and then show a set of representative equivalence rules. Since our equivalence checking method is based on potential internal equivalences identified by using random simulation, we also present how to prove the equivalence based on such potential internal equivalences. Finally, we explain our implementation of the rule-based equivalence checker and demonstrate its feasibility and e.ciency using an example design.

作者: Hiroaki Yoshida Masahiro Fujita

作者单位: VLSI Design and Education Center (VDEC), University of Tokyo CREST, Japan Science and Technology Agency

会议类型: 国际会议

会议名称: 2009国际通信电路与系统学术会议(ICCCAS 2009)(2009 International Conference on Communications，Circuits and Systems)

会议地点: 成都

会议语种:英文

页码: 1139-1143

在线出版日期: 2009-07-23（万方平台首次上网日期，不代表论文的发表时间）