Integration of High-Level Synthesis in ESL Platform Modeling by Automated Generation of Protocol Adapters
In this paper we present an approach for integrating IP components into a general system-level simulation environment by generating tailor-made interfaces and protocol adaptors. With the same methodology we integrate modules modeled for a certain high-level synthesis tool. For modeling systems-on-chip (SoC) interconnects e.g. buses at transaction level we use a generic communication architecture. An essential benefit of our approach is the capability for automatic adaptor generation by mapping component protocols onto a generic protocol which handles communication data and timing. For an independent system integration flow we use the standardized IP exchange format IP-XACT with protocol specific extensions as input for the generation process. In this context we introduce our generic architecture model for component integration in SystemC TLM 2.0 as well.
Jochen Zimmermann Oliver Bringmann Axel Braun Wolfgang Rosenstiel
Microelectronic System Design FZI Research Center for Information Technology 76131 Karlsruhe, German Department of Computer Engineering University of Tuebingen 72076 Tuebingen, Germany
国际会议
2009国际通信电路与系统学术会议(ICCCAS 2009)(2009 International Conference on Communications，Circuits and Systems)
成都
英文
1149-1154
2009-07-23（万方平台首次上网日期，不代表论文的发表时间）