A Real-time Interactive Verification System for ASIC Design

摘要：

The verification takes over 70％ of the whole workload in design of digital chips, especially the chips for communications. Practically, the FPGA verification is common used because the simulation verification is low-efficient. But it is not a perfect substitute for the simulation verification. So the method to improve the efficiency of the simulation should be investigated. The verification system proposed in this paper has been used in the verification work of the chips of the Dual-system navigation receivers baseband circuit. The verification methods in the system reduce the debug time, which are separating the part of the verification process to avoid the repetition and providing the real-time interactive interface to the designer.

关键词： simulation system ASIC verification real-time inteactive interface

作者: Linlin Su Xiaolin Zhang

作者单位: School of Electronic and Information Engineering, Beijing University of Aeronautics and Astronautics Beijing, China

会议类型: 国际会议

会议名称: 2009 WASE International Conference on Information Engineering(2009年国际信息工程会议)(ICIE 2009)

会议地点: 太原

会议语种:英文

页码: 431-434

在线出版日期: 2009-07-10（万方平台首次上网日期，不代表论文的发表时间）