A new parallel algorithm for analog circuit simulation
Parallel simulation is an efficient strategy to accelerate the simulation process for the analog circuit designs with increasing size. In this paper, low communication and coarse grain parallelization are concerned to achieve good performance on network of workstations. First, to split differential/algebraic system presenting the electronic circuit into sub-blocks, we present an efficient partitioning technique to produce sub-blocks with few interconnections. Second, for minimizing communication between the partitions, a set of evaluation factors are defined and a new static load balancing algorithm is proposed. At last, a practical circuit is taken to demonstrate the speedup of the parallel algorithm.
parallel computing circuit simulation static scheduling network of workstions
Jiafang Wang
School of Computer Science and Technology Heilongjiang University Harbin, China
国际会议
2009 WASE International Conference on Information Engineering(2009年国际信息工程会议)(ICIE 2009)
太原
英文
788-789
2009-07-10（万方平台首次上网日期，不代表论文的发表时间）